1. Field of the Invention
The present invention is directed toward an improved manufacturing process for a producing an isolated planar high speed PIN photodiode.
2. Description of the Related Art
Photodiodes are diodes in which charge carriers are generated responsive to light incident upon the photodiode. Any PN junction diode which admits light can function as a photodiode. A photodiode outputs voltage or current when absorbing light. In a photodiode which is intended for high speed communication systems, it is important to optimize the performance for light conversion efficiency, speed (minimal transit time delay), minimum RC time constant, ability to operate at low reverse bias voltage, and cost in the application in which the photodiode will be employed.
FIG. 1 illustrates the structure of a conventional PIN photodiode 10. A wafer 12 is lightly doped with N dopant in order to produce an intrinsic region 16. A P+ region 14 is formed on one surface of the wafer and an N+ region 18 is formed on the opposing surface of wafer 12 with intrinsic region 16 interposed P+ region 14 and N+ region 18. A reflective layer 20 is disposed on the surface containing N+ region 18 with reflective layer 20 also acting as the electrical contact to N+ region 18. A metal contact ring 22 is disposed on the surface containing P+ region 14 to provide the electrical connection to the P+ region.
Typically, one power supply potential is applied to the reflective layer and another power supply voltage is applied to contact 22 to reverse bias the PN junction formed by P+ region 14 and N+ region 18. This forms a depletion region 17 within the intrinsic region 16 wherein electron and hole charge carrier pairs generated by light photons incident upon the intrinsic region 16 are rapidly accelerated toward the P+ and N+ regions respectively by the electric field of the reverse bias voltage. Charge carrier pairs are also typically generated outside the depletion region 17 in non-depletion regions 24A and 24B of intrinsic region 16 and diffuse, due to random thermal motion of the carriers, at a much slower velocity until they reach either depletion region 17 or the junction formed by P+ region 14 and intrinsic region 16 of photodiode 10.
A conventional photodiode that is designed for high quantum, i.e. light conversion, efficiency requires that the light path within the photo current collection zone, the non-depletion 24 and depletion 17 regions, be sufficient in length so that most of the light photons of the incident light signal are absorbed and converted into electronhole pairs that are collectable at the P+ and N+ regions. Usually, this requires that the width W2 of the intrinsic region 16, which is the primary collection region between the P+14 and N+18 regions, be several times the length required for light absorption. If diode 10 has an efficient back-side reflector, such as reflective layer 20, which effectively doubles the light path within diode 10, then the intrinsic region 16 of the photodiode can be made narrower. For a typical near infrared silicon photodiode, the nominal absorption path length is about 15-25 microns. The path length should be at least two to three times the nominal absorption path length to obtain good light conversion efficiency.
On the other hand, a photodiode designed for high frequency response requires that the photo current pairs generated by the light signal be collected rapidly and that the diode RC time constant is fast. Rapid photo current pair collection usually requires that most of the photo current pairs generated by the light signal be generated within the depletion region 17 which has a high drift velocity when reversed biased. Otherwise, the photo generated charge carrier pairs produced in the non-depletion regions 24A and 24B outside the depletion region 17, but within the diffusion distance of the collection electrodes 14 and 18, will have a diffusion velocity which is several hundred times slower than the velocity of the pairs generated within the depletion region 17. The photo generated charge carrier pairs in non-depletion regions 24A and 24B will slowly migrate for collection at P+ region 14 and N+ region 18 resulting in a tail on the trailing edge of the electrical signal corresponding to the light signal. The diffusion distance of the charge carriers is determined by the carrier mean free path before re-combination and may exceed 150 microns.
A fast RC time constant for photodiode 10 requires minimal capacitance and low series resistance between the electricals contacts 20 and 22 and the photo current pair collection sites at the margin between the depletion region 17 and P+ region 14 and the margin between depletion region 17 and N+ region 18. The greater the width W2 of the depletion layer 16, then the lower will be the capacitance per unit area of photodiode 10. Since the depletion width of the depletion region formed between P+ region 14 and N+ region 18 increases with the level of the reverse bias voltage, it is typical for high speed photodiodes to have a relatively high reverse voltage applied to them.
The inclusion of the separate lightly doped intrinsic region 16 between the P+ and N+ regions 14 and 18 results in a PIN diode with a wider depletion region 17, depending on reverse bias voltage, which improves the light collection efficiency, speed, and reduces capacitance over that of a simple PN photodiode structure. Tailoring the width of the intrinsic region 16 allows for enhanced performance and tradeoffs for photodiode light conversion efficiency, response speed, and capacitance.
For example, a near infrared photodiode intended for use in a high speed, low cost IrDA data receiver operating from a 2.7V-5V power supply should ideally have an intrinsic layer width W2 of about 20-40 microns wide to allow for good light absorption efficiency and to allow for full depletion of the intrinsic region 16 with a low 1-3V reverse bias, since typically not all of the power supply voltage is available for reverse bias. Such a diode will achieve minimal transit delay, less than 1 nanoseconds (ns), a minimal RC time constant, and optimal high current frequency response with low resistance in the intrinsic region 16.
Although a PIN photodiode outperforms a standard PN diode, it cannot be easily manufactured by standard semiconductor processes wherein fabrication is typically performed on only one side of the semiconductor wafer 12.
A PIN photodiode is typically produced by diffusing the N+ diffusion region 18 on the back side of the lightly doped (N) wafer 12, diffusing the P+ diffusion region 14 on the topside of wafer 12, and then adding metal contacts to each side of the wafer. Typically, the backside contact area connected to N+ region 18 is reflective layer 20 and is made of gold. The topside contact area 22 is an aluminum collector ring that is connected to P+ diffusion region 14. The intrinsic or depletion layer depth W2 is determined by the wafer starting thickness W1 less the thickness of the N+18 and P+14 diffusion regions. Since standard silicon wafers are 350-500 microns in thickness and N+ and P+ diffusions are only a few microns thick, this typically results in an intrinsic layer width W2 of 345-495 microns.
An improvement to the PIN manufacturing process described above is to lap the width W1 of the starting wafer 12 to as thin as 100 microns, which will reduce the intrinsic layer width W2 to about 95 microns. However, it is generally not practical to thin wafers beyond this limit without an excessive level of wafer breakage along with severe wafer handling and processing problems.
A PIN diode with an intrinsic region width W2 of 95 microns typically requires more than a 5V reverse bias to be applied to the P+ and N+ regions 14 and 18 in order to completely deplete the intrinsic region 16 and achieve optimal frequency response for the photodiode. Consequently, the use of such a PIN photodiode in a high speed data receiver operating from a standard power supply voltage level of 2.7V-5V results in degraded speed performance.
Another problem with the structure of PIN diode 10 is that the connection of reflective layer 20 on the backside of wafer 12 requires the conductive bonding of the die of photodiode to a conductive substrate which may not be at the desired power supply potential or may not be a convenient electrical connection in the receiver design. In addition, if this conductive substrate is the active output of a photodiode it may undesirably act as an antenna for noise pickup.
Another method which has been attempted to produce a low cost PIN diode is to grow an epitaxial intrinsic layer on top of an N+ or P+ diffusion. However, because such an epitaxial layer is grown at high temperature it has high auto-doping levels due to the diffusion of the dopants of the underlying diffusion region which consequently prevents the formation of a lightly doped intrinsic layer 16.
Another method for producing a PIN diode 10 that is more successful is to grow an insulating oxide layer on top of the N+ or P+ diffusion and then to grow a thick polysilicon layer of several hundred microns to act as a handling layer so that the wafer 12 may be lapped as thin as needed to obtain the desired intrinsic region width W2. Following the lapping operation, the PIN diode can be processed in the standard way. Although this method is proven effective, growing a thick polysilicon layer is an expensive processing step.
One problem with the structure of PIN photodiode 10 is that the junction between the P+ region 14 and intrinsic region 16 does not extend to the edge of the photodiode. This is done in order to prevent shorting of the junction to the intrinsic region when cutting wafer 12 to obtain the individual die for each photodiode. Consequently, the depletion region 17 produced by the reverse bias voltage does not fully extend to the edge of the die resulting in non-depletion regions 24A and 24B at the edge of photodiode 10 which can be significant sources of slow diffusing photo generated carriers. A metal light guard ring is typically placed over the edge region of photodiode 10 to minimize generation of carriers in drift regions 24A and 24B, but this does not filly suppress the formation of slow carriers.
Accordingly, it is an object of the present invention to reliably produce a PIN photodiode having high speed operation at low operating voltages.
The present invention describes several improved methods utilizing standard IC processing technology, V-groove or trench etching technology, lapping technology, combined with the novel use of a handling wafer to produce a PIN diode featuring 1) an arbitrarily thin intrinsic region which can be depleted at a low operating voltage, 2) improved dielectric isolation of the backside of the photodiode from the mounting substrate, and 3) full dielectric isolation of the side walls which ensures the complete depletion of the active region and totally preventing the generation of slowly diffusing carriers.
An embodiment of a method, according to the present invention, for fabricating a PIN photodiode calls for providing a first semiconductor substrate lightly doped with a first dopant type, where the first semiconductor substrate has first and second planar surfaces. A first active region is formed by diffusing the first planar surface of the first semiconductor substrate with the first dopant type. A first oxide layer is formed on the first planar surface of the first semiconductor substrate. A first glass layer is formed on a first planar surface of a second semiconductor substrate. The first surface of the second semiconductor substrate is then bonded to the first planar surface of the first semiconductor substrate. The second planar surface of the first semiconductor substrate is then lapped. A second active region is formed by selectively masking and diffusing a predetermined portion of the second planar surface of the first semiconductor substrate with a second dopant type. A second oxide layer is formed on the second planar surface of the first semiconductor substrate that is then selectively masked and etched to form a first contact hole and an etching opening. The etching opening in the second oxide layer is then selectively etched down to the first oxide layer to form an isolation trench. A first contact is formed within the first contact hole. In another embodiment of a process according to the present invention, a polysilicon layer is formed on the first glass layer. In yet another embodiment of a process according to the present invention, a second glass layer is formed on a second planar surface of the second semiconductor substrate.